Developing Efficient Implementations of Shortest Paths and Page Rank Algorithms for NEC SX-Aurora TSUBASA Architectureстатья
Статья опубликована в журнале из списка RSCI Web of Science
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Статья опубликована в журнале из перечня ВАК
Статья опубликована в журнале из списка Web of Science и/или Scopus
Дата последнего поиска статьи во внешних источниках: 11 августа 2020 г.
Аннотация:The main goal of this paper is to demonstrate that the newest generation of NEC SX-Aurora TSUBASA architecture can perform large-scale graph processing extremely efficiently. This paper proposes approaches, which can be used for the development of high-performance vector-oriented implementations of page rank and shortest paths algorithms, including vectorised graph storage format, efficient vector-friendly graph traversals, optimised cache-aware memory accesses and efficient load-balancing. The developed implementations are optimised according to the most important features and properties of SX-Aurora architecture, which allows them achieve up to 15 times better performance compared to the optimised Intel Skylake parallel implementations and up to 5 times better performance compared to NVGRAPH library implementations for Pascal GPU architecture.