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The Method of Timing Optimization for FPGA at the Microarchitecture Level Using the Pipelining Mechanismстатья Исследовательская статья
- Авторы: Zheleznikov D.A., Lyalinsky A.A.
- Журнал: Проблемы разработки перспективных микро- и наноэлектронных систем МЭС
- Том: 3
- Год издания: 2017
- Издательство: Институт проблем проектирования в микроэлектронике РАН
- Местоположение издательства: Москва
- Первая страница: 58
- Последняя страница: 62
- Аннотация: In the article the method of timing optimization using pipelining mechanism for combinational circuits designed on FPGA, is presented. Pipelining method using retiming technique for combinational circuits is known. However, this approach is limited because of feedback loops: the more of them in the initial circuit, the less efficiency of the technique. It should be noted that the method is used for a fixed time graph and it does not consider its changing due to variations of load and parasitic capacitances, as well as the length of the wires because of registers movement. Thus, it has relatively low accuracy on real circuits. In this paper we present a method of combinational circuits pipelining based on iterative insertion of additional registers to reduce the length of critical paths in the time graph and achieve the desired operating frequency. In the first step the time graph is constructed by static timing analysis methods. After that, the critical path searching by classical algorithm of Kirkpatrick is performed. The method is focused on practical use and can be included in the general FPGA design flow. In this article, description of method usage is given; a simple practical example is shown.
- Добавил в систему: Железников Даниил Александрович